Recent Publications

More Publications

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    A Highly Efficient Layout-Aware FPGA Overlay Accelerator Mapping Method, IEEE 14th International Symposium on Embedded Multicore/Many-core System-on-Chip (MCSoC).
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    MN-Core - A Highly Efficient and Scalable Approach to Deep Learning 2021 Symposia on VLSI Technology and Circuits (VLSI).
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    Reducing underflow in mixed precision training by gradient scaling, 29th International Conference on International Joint Conferences on Artificial Intelligence (IJCI).
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    Accuracy-Aware Memory Allocation to Mitigate BRAM Errors for Voltage Underscaling on FPGA Overlay Accelerators, 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA).

Patents


  • The data transfer method of a processor and processor, JP Patent App. 2018-211312.

  • Processor and control method for processor, US Patent App. 17/447,316.

  • Processor with processing cores each including arithmetic unit array, US Patent 16/671,428.
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    Semiconductor device and circuit layout method, US Patent App. 17/199,587.
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    Semiconductor device, circuit arrangement method, circuit arrangement program and recording medium, JP Patent App. 2020-45750.
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    Method and apparatus for training neural network, US Patent App. 17/073,517.

  • Data compression method, data compression apparatus, data decompression method, data decompression apparatus and data storage syste, US Patent App. 16/838,343.

  • Optimization apparatus and method for controlling thereof, US Patent App. 16/284,123.

  • The control method of the optimization device and optimization apparatus, JP Patent 2018-47655.